1. Field of the Invention
This invention relates to the planarization of semiconductor devices by Chemical-Mechanical-Polishing (CMP) techniques and, more particularly, to the formulation of polishing slurries for metals and oxides where the rate of polishing allows both metal and oxide to be removed simultaneously. By use of the slurry of the invention process costs can be reduced and semiconductor wafers can be successfully reclaimed and re-processed.
2. Description of the Prior Art
Chemical-Mechanical-Polishing techniques are used in the semiconductor processing industry to enable interconnect metallurgy of the highest density to be fabricated. Based on the teachings in U.S. Pat. No. 4,789,648 to Chow et al. and U.S. Pat. No. 4,944,836 to Beyer et al., CMP has enabled the continued shrinking of semiconductor device dimensions by the practical and manufacturable introduction of planarization of metals or interlevel dielectrics to semiconductor processing. By maintaining the surface of a semiconductor device as flat as possible, the rendering of optical images of ever smaller size continues to be possible.
CMP technology used for planarization of inter-level dielectric (ILD) is usually performed in a strong basic solution having a high pH and relies heavily on the abrasive effects of silica particles. Technology for metals generally is based on the principles that most hard materials are reactive with oxidants to form oxides and other softer compounds which, in turn, can be polished away. As such the slurries used are usually strongly acidic and have low pH. If the process of reacting and polishing can be controlled sufficiently, semiconductor metallurgy will continue to lead the path to miniaturization.
In most CMP processes great effort is expended to increase the selectivity of a slurry between two materials present in the polishing environment. For example, if one is attempting to remove tungsten from an oxide layer, the preferred slurry would polish tungsten many times faster than oxide. The reverse is usually true when polishing oxides over metal layers.
It is known to planarize tungsten metallurgy by polishing with an aqueous slurry comprising alumina in ferric nitrate. See "PROCESS OPTIMIZATION OF TUNGSTEN CMP." V. Blaschke and K. Holland, Chemical Mechanical Polishing--Metals Seminar (CMP), SEMICON/Southwest '95; Austin, Tex.; Oct. 23, 1995. This slurry, when used in an IPEC-Westech Systems wafer polisher at a feedrate of about 125 ml per minute, has the capability of polishing tungsten at 3,000 Angstroms per minute. The slurry, however, has the following disadvantages:
1. The alumina colloidal suspension is unstable and the ferric nitrate solution must be agitated constantly to keep the suspension dispersed in the solution. If left alone, the suspension collapses within a few hours rendering it impossible to formulate batches of slurry in advance. The settling of the alumina particles indicates that the particles are not well dispersed at all, a condition which could easily lead to scratching and cause other polishing irregularities since the slurry actually contains particulates and agglomerates large enough to settle out of suspension. This also can cause Foreign Material (FM) problems and loss of product yield.
2. The polishing slurry leaves rust residue on items throughout the CMP tool area. Whenever some slurry is spilled or sprayed, orange rust is left behind when the slurry dries. The stains are an indication that the ferric ion is prone to polymerizing to oxo-bridged species, leading to ferric-bearing oxide residues. These residues are a source of FM. The polymerization can also account for agglomeration of the alumina, as the polymerized ferric species likely promotes adhesion of alumina particles to each other. This condition often causes tools to be shut down for cleaning and removal of slurry cakes by the use of a hammer.
3. The heterogenity of the slurry also prohibits the bulk feeding of the slurry to the tools. Because the particulates in the slurry have a tendency to settle out, the particulates will precipitate out within any delivery system clogging tubing and valves.
4. The tendency of the ferric components to form rust residue causes corrosion wherever the slurry lands and dries on stainless steel parts of the polishing tools. This is a cause of FM problems and eventually destroys polisher components.
Other ferric-based salts have been proposed and include potassium ferricyanide as an oxidizer, combined with an acetate buffer and acetic acid using a silica abrasive as described in U.S. Pat. No. 5,407,526 to Danielson et al. and U.S. Pat. No. 5,516,346 to Cadien et al.
U.S. Pat. No. 5,527,423 to Neville et al. describes a polishing slurry for selectively polishing metals. The slurry includes ferric nitride nonahydrate and deionized water in which a special fumed alumina or silica is used to provide stability of particles in suspension. The disclosure also suggests other additives and stabilizers which may be added immediately prior to use. The differences in polish rates obtained are attributed to the high surface area finned silica or alumina of the invention and the resulting slurry suitable for most metals
Oxide slurries, see U.S. Pat. No. 4,944,836 to Beyer et al., are usually basic and may contain a bout 1 to 10% by weight silica in potassium hydroxide, for example. Recently acid stabilized silica slurries have become available, but these still exhibit instability when additional reagents are added to the slurry as surfactants or other surface controlling agents.
A typical planarized Back-End-Of-the-Line (BEOL) Field Effect Transistor (FET) process includes the following steps, as an example.
A semiconductor wafer is processed up through the gate electrode and a first dielectric passivation layer. Via holes are formed and a contact metal is provided in the holes. Processing to this point in the process may or may not provide a planarized surface.
Following the initial process steps, an ILD layer, usually a phosphorous or boron containing glass is deposited. The ILD layer is planarized by CMP technology selective to the deposited ILD layer. The planarization is followed by the etching of via holes or both via holes and lines in the ILD layer.
A metal, including any desired contact enhancing or barrier providing layer, is blanket deposited. The metal layer is then planarized by a CMP process selective to the metal with respect to the ILD. This step leaves either exposed metal studs coplanar with the top of the ILD or, in the case of dual Damascene processing, metal lines coplanar with the top of the ILD layer.
If dual Damascene is not practiced, a metal layer for the lateral interconnects between studs is deposited and etched to define the level of metal, usually designated Mn where n is the number of the level above the substrate. In the case of dual Damascene, the Mn level is part of the deposited and planarized metal already deposited.
U.S. Pat. No. 4,956,313 to Cote et al. teaches a process in which the planarization following the first ILD layer may be omitted and a slurry comprising 40 grams of alumina in 10 liters of deionized water to which strong oxidizing agent, hydrogen peroxide, and a strong base, potassium hydroxide, is added adjusting the pH to 8.4. Selectivity of oxide to tungsten was about 200/300 Angstroms per minute and produced coplanar polished layers.
M. A. Jaso, in his published European application EP 0 773 580 A1 published Oct. 21, 1996, teaches a post tungsten slurry comprising fumed colloidal silica, 8% wt, and 20 g/l ammonium persulfate which is said to be non-selective between tungsten and oxide.
A major problem presented to manufacturers is that of reworking of product because some aspect of a process has been unacceptably performed. Reworking of BEOL processes are quite well known and are represented by the following references.
U.S. Pat. No. 4,415,606 to Cynkar et al. teaches a rework process for metallurgy in which portions of deposited and etched metal are selectively etched from a substrate.
The article, "Rework Process for Integrated Circuit Chip Pads," Annon., IBM Technical Disclosure Bulletin, Vol. 37, No.01, January 1994, p 333, teaches rework process in which each added layer is removed in turn by a process selective to that material.
The article, "ALUMINUM METALLURGY REWORK PROCESS," Anon., IBM Technical Disclosure Bulletin, Vol. 33, No.4, September, 1990, p.240, teaches that rework can be accomplished by first selectively etching away an aluminum line and then using CMP to remove the ILD layer.
The article, "MULTIPLE LEVEL INTEGRATED CIRCUIT REWORK USING CHEMICAL MECHANICAL POLISH AND REACTIVE ION ETCHING," Annon., IBM Technical Disclosure Bulletin, Vol. 35, No.1 B, June 1992, pp 254-5, teaches the use of an reaction ion etching (RIE) tool to remove oxide followed by CMP or RIE to selectively remove the metal.
U.S. Pat. No. 4,879,257 to Patrick teaches a method of coplanarizing metal, photoresist and ILD layers simultaneously using RIE or plasma etching.
U.S. Pat. No. 5,142,828 to Curry, II teaches the reworking of a BEOL processed wafer where the ILD is a polyimide polymer and the metal is copper by polishing with a slurry including only silica in water.